Semiconductor device and system having semiconductor device mounted thereon

ABSTRACT

There is provided a semiconductor device that is capable of reducing wring density of the wiring pattern on a mounting board on which it is mounted, thereby facilitating routing of the wiring pattern. Pads are formed which are connected to pads on a bare chip by bonding wires. There are formed vias extending from the respective pads to a bottom surface of a package, and vias extending from the respective pads to a top surface of the package. This makes it possible to connect the mounting boards to the top and bottom surfaces of the package, thereby enabling reduction of the wiring density of wiring patterns on the mounting boards, thereby facilitating routing of the wiring patterns on the mounting boards.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 10/385,919filed Mar. 11, 2003, now pending, which claims priority from JapanesePatent Application 2002-195650 filed Jul. 4, 2002, the contents of whichare herein incorporated by reference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to a semiconductor device and a system having thesemiconductor device mounted thereon, and more particularly to a ballgrid array packaged semiconductor device and a system having the ballgrid array packaged semiconductor device mounted thereon.

(2) Description of the Related Art

These days, with the progress of higher integration of elements intosemiconductor devices, each semiconductor device has an increasingnumber of connection pins for connection to a mounting board. Further,to reduce the area of the semiconductor device, a narrower pin pitch isemployed.

Packages of semiconductor devices include a QFP (Quad Flat Package), anSQFP (Shrink Quad Flat Package), and so forth. However, these packagesare limited in their capability of coping with increase in the number ofconnection pins and reduction in the area of the semiconductor device.To overcome the problem, recently, attention has come to be paid to aBGA (Ball Grid Array) package allowing a large number of connection pinsto be arranged thereon.

A BGA packaged semiconductor device includes connection pins (pads) onthe underside of the package. FIG. 16 is a cross-sectional view of aconventional BGA packaged semiconductor device. The figure shows thesemiconductor device 100, and a mounting board 110 on which thesemiconductor device 100 is mounted. The semiconductor device 100 ismounted on the mounting board 110 by solder balls 111.

The semiconductor device 100 is comprised of the package 101, an innerboard 102 fixed to an inner wall of the package 101 toward the mountingboard 110, cylindrical vias 103 extending through the inner board 102 tothe underside of the package 101, a bare chip 104 fixed to the innerwall of the package 101 toward the mounting board 110, and bonding wires105 connecting the bare chip 104 and the vias 103 to each other.

Each via 103 has a pad 103 a formed at one end thereof on the side ofthe inner board 102 for connection to one of the bonding wires 105, anda pad 103 b formed at the other end thereof on the side of the mountingboard 110 for connection to the wiring pattern on the mounting board 110via one of the solder balls 111. The bare chip 104 have pads 104 a forconnection to the bonding wires 105.

Signal lines routed on the top of or inside the bare chip 104 areconnected to the respective pads 104 a to allow connection thereto. Thepads 104 a and the pads 103 a of the vias 103 are connected by thebonding wires 105. The pads 103 b of the vias 103 are connected to thewiring pattern on the mounting board 110 via the solder balls 111. Thus,the semiconductor device 100 has its signal lines provided withrespective conductive extensions leading only to the underside of thepackage 101 toward the mounting board 110.

Incidentally, some BGA packaged semiconductor devices have 800connection pins (pads 103 b of the vias 103 in FIG. 16), and furthersome have a pin pitch of 0.8 mm. A semiconductor device of this kindwith a large number of connection pins is mounted on a build-up board ora multi-layer board comprised of a lot of layers.

However, the semiconductor device is further making a progress towardstill higher integration of elements therein, resulting in an evenlarger number of connection pins provided thereon. This increases thewiring density of a wiring pattern on a mounting board, which makes thewiring pattern difficult to be routed.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above circumstances,and an object thereof is to provide a semiconductor device which makesit possible to reduce wiring density of a wiring pattern on a mountingboard, thereby facilitating routing of the wiring pattern.

To attain the above object, there is provided a ball grid array packagedsemiconductor device. This semiconductor device is characterized bycomprising pads fixed within a package and connected to signal lines ofa bare chip, and vias extending from associated ones of the pads to abottom surface and a top surface of the package.

The above and other objects, features and advantages of the presentinvention will become apparent from the following description when takenin conjunction with the accompanying drawings which illustrate preferredembodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinal sectional view of a semiconductor deviceaccording to a first embodiment of the present invention.

FIG. 2 is an exploded view of the semiconductor device.

FIG. 3 is a view of the FIG. 2 semiconductor device after beingassembled.

FIG. 4 is an exploded view (second one) of a semiconductor device.

FIG. 5 is a view of the FIG. 4 semiconductor device after beingassembled.

FIG. 6 is a view showing a semiconductor device before molding of anupper package.

FIG. 7 is a diagram showing the semiconductor device after molding ofthe upper package.

FIG. 8 is a perspective view of semiconductor devices and mountingboards.

FIG. 9 is a perspective view of semiconductor devices, mounting boards,and flexible boards.

FIG. 10 is a cross-sectional view of semiconductor devices which aredirectly connected to each other and mounted on mounting boards.

FIG. 11 is a cross-sectional view of a semiconductor device and bypasscapacitors.

FIG. 12 is a view useful in explaining a method of mounting thesemiconductor device.

FIG. 13 is a view useful in explaining a method (second one) of mountingthe semiconductor device.

FIG. 14 is a longitudinal sectional view of a semiconductor deviceaccording to a second embodiment of the present invention.

FIG. 15 is a longitudinal sectional view of a semiconductor deviceaccording to a third embodiment of the present invention.

FIG. 16 is a cross-sectional view of a conventional BGA packagedsemiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will now be described in detail with reference to thedrawings showing a preferred embodiment thereof.

FIG. 1 is a longitudinal sectional view of a semiconductor deviceaccording to a first embodiment of the present invention. Thesemiconductor device shown in FIG. 1 is comprised of a package 2, a barechip 3 fixed to a central portion of an inner bottom surface of thepackage 2, an inner board 4 fixed to the inner bottom surface of thepackage 2 in a state fitted to the periphery of the bare chip 3, pads 5fixed to an upper surface of the inner board 4 and connected to signallines of the bare chip 3, respectively, vias 6 a extending from therespective pads 5 to an outer bottom surface of the package 2, vias 6 bextending from the respective pads 5 to an outer top surface of thepackage 2, bonding wires 7 for connecting the bare chip 3 and the pads5, and a mold 8 filled within the package 2.

The bare chip 3 has pads 3 a formed on a top surface thereof forconnection to the respective bonding wires 7. The signal lines routed onthe top of or inside the bare chip 3 are connected to the pads 3 a,respectively, to allow connection thereto. The pads 3 a on the topsurface of the bare chip 3 and the pads 5 are connected by the bondingwires 7, respectively.

The vias 6 a, 6 b have cylindrical via pads 6 aa, 6 ba on the outerbottom surface and the outer top surface of the package 2, respectively,for connection to respective wiring patterns on mounting boards viasolder balls.

As described above, each pad 5 connected to the signal line of the barechip 3, and the respective vias 6 a, 6 b extending from the pad 5 to theouter bottom surface and outer top surface of the package 2 are arrangedsuch that each signal line of the bare chip 3 is provided withrespective conductive extensions leading to the outer bottom surface andouter top surface of the package 2. This makes it possible to connectthe mounting boards to the top and bottom surfaces of the package 2 toreduce wiring density of the wiring pattern on each mounting board,thereby facilitating routing of the wiring pattern.

Further, the reduction of the wiring density reduces the number of viaholes in each mounting board, which makes it possible to increase thenumber of semiconductor devices to be mounted.

It should be noted that pads for connection to the bonding wires 7 maybe arranged on the inner board 4 around the bare chip 3, with a wiringpattern formed in an inner layer within the inner board 4, forconnection between these pads and the pads 5. This also makes itpossible to electrically connect the signal lines of the bare chip 3 andthe pads 5, thereby providing the signal lines of the bare chip 3 withconductive extensions leading to the outer top surface and outer bottomsurface of the package 2.

Next, a method of manufacturing the semiconductor device will bedescribed hereafter.

FIG. 2 is an exploded view of the semiconductor device. As shown in thefigure, the package 2 of the semiconductor device 1 is divided into alower package 2 a and an upper package 2 b. The package 2 is formed of aceramic material.

The lower package 2 a and the inner board 4 are formed with holes thatallow the vias 6 a to be fitted therein. The vias 6 a are fitted intothe holes formed through the lower package 2 a and the inner board 4from an outer bottom surface of the lower package 2 a. The length ofeach via 6 a is configured to be equal to the thickness of the lowerpackage 2 a and the inner board 4 measured from the outer bottom surfaceof the lower package 2 a to the upper surface of the inner board 4.

Each pad 5 is formed by molding with a resist or the like, at a portionof the inner board 4 where the via 6 a is driven. The pad 5 and acorresponding one of pads 3 a on the top surface of the bare chip 3 areconnected by the bonding wire 7. It should be noted that the inner board4 is made of glass epoxy or the like.

Each via 6 b is integrally formed with the upper package 2 b by moldingwhen the upper package 2 b is molded. The vias 6 a, 6 b, and the pads 5are made of copper, for instance. The pads 5 are plated with gold.

The lower package 2 a and the upper package 2 b are joined to eachother. FIG. 3 shows an assembled state of the FIG. 2 semiconductordevice. When the lower package 2 a and the upper package 2 b are joinedto each other, the via 6 b has a length which is large enough for a tipof the via 6 b to reach the pad 5 and at the same time not so long as tobe broken by the joining. In short, the via 6 b is brought into pressurecontact with the pad 5 by joining of the lower package 2 a and the upperpackage 2 b.

Further, when the lower package 2 a and the upper package 2 b are joinedto each other, the mold 8 is injected therebetween to seal the inside ofthe package 2. As the material of the mold 8, there is used aluminumsilicon, aluminum nitride ceramics or the like.

It should be noted that to seal the inside of the package 2, a hermeticsealing method is employed which hermetically seals the inside of thepackage 2 from the outside thereof to prevent intrusion of even a verysmall amount of gases or moisture. The hermetic sealing method isclassified into metal sealing, ceramic sealing, solder sealing, etc.according to the material used. Further, a non-hermetic sealing methodcan be employed which is typified by a transfer mold method low in costand excellent in mass productivity, though incapable of providing suchhigh hermeticity as the hermetic sealing method.

As described above, it is possible to manufacture the semiconductordevice in which the upper package 2 b integrally formed with the vias 6b are joined to the lower package 2 a having the vias 6 a driven thereinsuch that the vias 6 b are brought into pressure contact with the pads5, thereby providing the signal lines of the bare chip 3 with conductiveextensions leading to the outer top surface and outer bottom surface ofthe package 2.

It is also possible to manufacture the semiconductor device by formingthe vias 6 a, 6 b in the lower package 2 a and then joining the upperpackage 2 b to the lower package 2 a. FIG. 4 is an exploded view (secondone) of the semiconductor device. As shown in the figure, the package 2of the semiconductor device 1 is divided into a lower package 2 a and anupper package 2 b, both of which are formed of a ceramic material.

Similarly to the case described above with reference to FIG. 2, thelower package 2 a and an inner board 4 are formed with holes into whichvias 6 a are driven to be fixed therein. Pads 5 to be brought intopressure contact with respective vias 6 b are formed by molding with aresist or the like, at portions of the inner board 4 where the vias 6 aare driven. Each pad 5 and a corresponding one of pads 3 a on a topsurface of a bare chip 3 are connected by a bonding wire 7. Each via 6 bis joined to the pad 5. The via 6 b is configured in advance to havesuch a length that the via 6 b slightly protrudes from the outer topsurface of the upper package 2 b when the lower package 2 a and theupper package 2 b are joined to each other.

Formed through the upper package 2 b are holes 2 ba having the sameshape as that of the pads 6 ba of the vias 6 b. The upper package 2 b isjoined to the lower package 2 a such that the pads 6 ba are fitted intothe holes 2 ba associated therewith, respectively. FIG. 5 shows anassembled state of semiconductor device shown in the FIG. 4. When thelower package 2 a and the upper package 2 b are joined to each other, amold 8 is injected therebetween to seal the inside of the package 2. Thematerial of the mold 8 and the sealing method of sealing the inside ofthe package 2 are the same as described hereinabove with reference toFIGS. 2 and 3, and hence detailed description thereof is omitted.

Respective portions of the vias 6 b (pads 6 ba) protruding from theupper package 2 b are cut off such that the top surface of each via 6 bis flush with the top surface of the upper package 2 b (forming of viaposts).

As described above, it is possible to manufacture the semiconductordevice by fixing the vias 6 a, 6 b to the lower package 2 a, and joiningthe upper package 2 b formed with the holes 2 ba having the same shapeas that of the pads 6 ba of the vias 6 b so as to have them fittedtherein, to the lower package 2 a, such that the signal lines of thebare chip 3 are provided with respective conductive extensions leadingto the outer top surface and outer bottom surface of the package 2.

Further, it is also possible to manufacture the semiconductor device bycovering the lower package having the vias fixed thereto with a mold,and then performing a sintering or coagulating process. FIG. 6 shows thesemiconductor device before molding of the upper package. Similarly tothe case described above with reference to FIG. 2, in this semiconductordevice 1, vias 6 a are fixed to a lower package 2 a and an inner board 4and pads 5 are formed on the vias 6 a by molding. Each pad 5 and acorresponding one of pads 3 a on a top surface of a bare chip 3 areconnected by a bonding wire 7. Each via 6 b is joined to the top of thepad 5.

The whole of the lower package 2 a is covered with a mold, and thesintering or coagulating process is carried out. The lower package 2 ais covered with the mold up to the height of the pads 6 ba of the vias 6b. As the material of the mold for the sintering or coagulating process,there is used a synthetic material of aluminum and silicon carbidehaving high thermal conductivity and high thermal expansion, or a resinmold. FIG. 7 shows the semiconductor device after molding of the upperpackage. As shown in the figure, the mold 8 a is formed into the upperpackage by the sintering or coagulating process.

As described above, it is possible to manufacture the semiconductordevice by fixing the vias 6 a, 6 b to the lower package 2 a, coveringthe whole lower package 2 a with the mold 8 a, and performing thesintering or coagulating process, such that the signal lines of the barechip 3 are provided with respective conductive extensions leading toboth the top and bottom surfaces of the package 2.

Next, mounting of the semiconductor device on the mounting board will bedescribed hereinafter.

FIG. 8 is a perspective view of semiconductor devices and mountingboards. The figure shows the semiconductor devices 1 a to 1 c accordingto the invention, a lower mounting board 11, an upper mounting board 12(part of which is omitted), and a CPU (Central Processing Unit) 13. Thesemiconductor devices 1 a to 1 c are mounted on the lower mounting board11 and the upper mounting board 12 via the top and bottom surfaces oftheir packages. Vias connected to the signal lines of the bare chips ofthe semiconductor devices 1 a to 1 c are connected to wiring patterns onthe lower mounting board 11 and the upper mounting board 12 according tothe kinds of signals. The CPU 13 is mounted on the lower mounting board11.

Now, let it be assumed, for instance, that the semiconductor devices 1 ato 1 c are DSPs (Digital Signal Processors), that each DSP has a localbus for transmitting and receiving address signals, data, and controlsignals only between the DSPs, and a bus of a PCI interface fortransmitting and receiving data between the same and the CPU 13, andthat a memory, not shown in FIG. 8, according to the semiconductordevice of the present invention, which is capable of inputting andoutputting data via the top and bottom surfaces of the package, ismounted between the lower mounting board 11 and the upper mounting board12. The package of the memory has pads formed on a top surface thereof,which are connected to the local buses of the DSPs, and pads formed on abottom surface thereof for supplying electric power and reset signals.It should be noted that if a memory having pads only in the bottomsurface of the package thereof is used, the memory may be mounted on theupper mounting board 12.

In the above case, the wiring pattern of the local buses are arranged onthe upper mounting board 12, and the wiring pattern for the PCIinterfaces are arranged on the lower mounting board 11. This makes itpossible to physically separate the local buses of the DSPs and the PCIbus of the CPU 13 from each other by using the upper and lower mountingboards, thereby preventing cross-talk and noise from being caused by thebuses. More specifically, the wiring patterns on the upper and lowermounting boards are made separate from each other according to the kindsof signals, and wired, whereby it is possible to prevent occurrence ofcross-talk and noise at the wiring patterns.

It should be noted that the signal lines and power lines of the lowermounting board and the upper mounting board may be directly connected toeach other by connectors or lead lines, neither of which is shown.

FIG. 9 is a perspective view of semiconductor devices, mounting boards,and flexible boards. The figure shows the lower mounting board 11, uppermounting boards 12 a to 12 c, and flexible boards 14 a, 14 b. Thesemiconductor devices, not shown, according to the present invention aremounted between the lower mounting board 11 and the upper mountingboards 12 a to 12 c. The flexible board 14 a is connected to the uppermounting boards 12 a, 12 b. The flexible board 14 b is connected to theupper mounting boards 12 b, 12 c.

As a result, for instance, even if the upper mounting boards 12 a to 12c are deflected by a force applied thereto from an upward direction or adownward direction, the deflection is absorbed by the flexible boards 14a, 14 b, thereby making it possible to prevent the upper mounting boards12 a to 12 c from being cracked.

More specifically, by causing the upper mounting boards to have thesemiconductor devices mounted thereon on a semiconductordevice-by-semiconductor device basis, and the wiring patterns on theupper mounting boards to be connected by the flexible boards, it ispossible to prevent breakage of the upper mounting boards.

It should be noted that the semiconductor devices may be mounted on themounting boards in a state directly connected to each other. FIG. 10 isa cross-sectional view schematically showing the semiconductor deviceswhich are mounted on the mounting boards in a state directly connectedto each other. The figure shows a lower mounting board 20 a, an uppermounting board 20 b, and semiconductor devices 1 d, 1 e according to thepresent invention. Pads 1 da arranged on the bottom surface of thepackage of the semiconductor device 1 d and the wiring pattern on thelower mounting board 20 a are connected to each other. Pads 1 dbarranged on the top surface of the package of the semiconductor device 1d and pads 1 ea arranged on the bottom surface of the package of thesemiconductor device 1 e are connected to each other. Pads 1 eb arrangedon the top surface of the package of the semiconductor device 1 e andthe wiring pattern on the upper mounting board 20 b are connected toeach other.

Let it be assumed, for instance, that the semiconductor devices 1 d, 1 ehave a master/slave relationship. In this case, the signal lines of abare chip connected to the pads 1 da, 1 db in the semiconductor device 1d, and the signal lines of a bare chip connected to the pads 1 ea, 1 ebin the semiconductor device 1 e can be arranged in the same manner,whereby data lines and address lines of the upper and lowersemiconductor devices can be directly connected to each other.

As described hereinabove, the direct connection between the upper andlower semiconductor devices makes it possible to transmit and receivesignals between the semiconductor devices without arranging dedicatedwiring on the mounting boards. This makes it possible to reduce wringdensity of the wiring patterns on the mounting boards, therebyfacilitating routing of the wiring patterns.

Next, the positional relationship between the semiconductor device andbypass capacitors will be described. The semiconductor device has bypasscapacitors each connected between power terminals so as to preventfluctuation of power supply and eliminate noise. In general, it ispreferred that bypass capacitors are connected at locations close to thesemiconductor device. FIG. 11 is a cross-sectional view of thesemiconductor device and bypass capacitors. As shown in the figure, thesemiconductor device 1 f according to the present invention is mountedon a lower mounting board 30 a, and an upper mounting board 30 b. Vias 1fa to 1 fd are for supplying the electric power.

The electric power is supplied from the wiring pattern 30 aa of thelower mounting board 30 a to the vias 1 fa, 1 fb, and the vias 1 fc, 1fd. The vias 1 fa to 1 fd are also connected to the wiring pattern onthe upper mounting board 30 b, so that the bypass capacitors 31 a, 31 bcan be mounted at locations close to the vias 1 fa to 1 fd of the uppermounting board 30 b. This makes it possible to efficiently preventfluctuation of power supply and eliminate noise.

Next, a method of mounting the semiconductor device on mounting boardswill be described. FIG. 12 is a diagram useful in explaining the methodof mounting the semiconductor device. The figure shows the semiconductordevice 1 g according to the present invention mounted on a lowermounting board 40 a, and an upper mounting board 40 b. The semiconductordevice 1 g has vias 1 ga each having solder balls 41 a, 41 b attachedthereto in advance. The solder balls 41 a on the bottom surface of thepackage of the semiconductor device 1 g are different from the solderballs 41 b on the top surface of the same in melting temperature. Solderballs having a melting temperature lower than that of the solder balls41 a on the bottom surface of the package are used as the solder balls41 b on the top surface of the package. The lower mounting board 40 aand the semiconductor device 1 g are passed through a reflow oven tomount the semiconductor device 1 g on the lower mounting board 40 a.

The semiconductor device 1 g mounted on the lower mounting board 40 aand the upper mounting board 40 b are passed through the reflow ovenwhose temperature has reached a temperature high enough to melt thesolder balls 41 b, to thereby mount the semiconductor device 1 g on theupper mounting board 40 b. At this time, since the melting temperatureof the solder balls 41 b mounted on the upper mounting board 40 b islower than that of the solder balls 41 a mounted on the lower mountingboard 40 a, the lower solder balls 41 a are not melted. Thus, themounting boards are mounted on the top and bottom surfaces of thesemiconductor device 1 g.

FIG. 13 is a diagram useful in explaining a method (second one) ofmounting the semiconductor device on mounting boards. The figure showsthe semiconductor device 1 h according to the present invention mountedon a lower mounting board 42 a, and an upper mounting board 42 b. First,solder balls 43 a are attached in advance to pads of vias 1 ha of thesemiconductor device 1 h toward the lower mounting board 42 a, whilepastes are attached in advance to pads of the vias 1 ha toward the uppermounting board 42 b. The lower mounting board 42 a and the semiconductordevice 1 h are passed through the reflow, whereby the semiconductordevice 1 h is mounted on the lower mounting board 42 a, as shown in FIG.13.

The solder balls 43 b are attached to lands of the upper mounting board42 b, which are to be connected to the vias 1 ha of the semiconductordevice 1 h, respectively. Solder balls having a melting temperaturelower than that of the solder balls 43 a used for mounting the device onthe lower mounting board 42 a are used as the solder balls 43 b. Thesemiconductor device 1 h mounted on the lower mounting board 42 a andthe upper mounting board 42 b are passed through the reflow whosetemperature has reached a temperature high enough to melt the solderballs 43 b, to thereby mount the semiconductor device 1 h on the uppermounting board 42 b. At this time, since the melting temperature of thesolder balls 43 b on the upper mounting board 42 b is lower than that ofthe solder balls 43 a on the lower mounting board 42 a, the solder balls43 a are not melted. Thus, the mounting boards are mounted on the topand bottom surfaces of the semiconductor device 1 h.

By configuring to attach the solder balls to the upper mounting board 42b, it is possible to avoid attachment of unnecessary solder balls to thetop surface of the semiconductor device when the semiconductor device isnot mounted on the upper mounting board.

Next, a second embodiment of the present invention will be described.FIG. 14 is a longitudinal sectional view of a semiconductor deviceaccording to the second embodiment of the present invention. Thesemiconductor device 50 shown in FIG. 14 is distinguished from that ofthe first embodiment in that vias, which have pads thereof connected tothe signal lines of the bare chip, respectively, each extend from itspad only in the direction of the lower package or in the direction ofthe upper package. In the figure, component parts and elements similarto those shown in the FIG. 1 are designated by identical referencenumerals, and detailed description thereof is omitted.

As shown in FIG. 14, the semiconductor device 50 includes pads 51 a, 51b connected to the pads 3 a of the bare chip 3 by the bonding wires 7,respectively, vias 52 a extending from the pads 51 a to the outer bottomsurface of the lower package 2 a, respectively, and vias 52 b extendingfrom the pads 51 a to the outer top surface of the upper package 2 b,respectively.

As described above, since the signal lines of the bare chip are providedwith respective conductive extensions each leading either to the lowerpackage 2 a or to the upper package 2 b alone, it is possible to reducewring density of the wiring patterns on the mounting boards, therebyfacilitating routing of the wiring patterns.

Next, a third embodiment of the present invention will be described.FIG. 15 is a longitudinal sectional view of a semiconductor deviceaccording to the third embodiment of the present invention. Thesemiconductor device 60 shown in FIG. 15 is distinguished from that ofthe second embodiment in that vias, which have pads thereof connected tothe signal lines of the bare chip, respectively, and each extend fromits pad both in the direction of the lower package and in the directionof the upper package are mixed with vias of the FIG. 14 type eachextending from its pad only in the direction of the lower package or inthe direction of the upper package. In the figure, component parts andelements similar to those shown in the FIG. 14 are designated byidentical reference numerals, and detailed description thereof isomitted.

As shown in FIG. 15, the semiconductor device 60 includes pads 61connected to the pads 3 a of the bare chip 3 by the bonding wires 7,respectively, vias 62 a extending from their pads 61 to the outer bottomsurface of the lower package 2 a, and vias 62 b extending from theirpads 61 to the outer top surface of the upper package 2 b. Further, thesemiconductor device 60 includes vias 52 a extending from their pads 51a through the lower package 2 a, and vias 52 b extending from their pads51 b to the upper package 2 b.

As described above, by providing the vias 52 a, 52 b extending fromtheir pads 51 a, 51 b connected to the signal lines of the bare chips 3only to the lower package 2 a and only to the upper package 2 b,respectively, and the vias 62 a, 62 b extending from the their pads 61both to the lower package 2 a and the upper package 2 b in a mixedmanner, it possible to reduce wiring density of the wiring patterns onthe lower and upper mounting boards, thereby facilitating routing of thewiring patterns on the boards.

As described hereinbefore, the semiconductor device according to thepresent invention is configured such that the vias extend from padsfixed within the package and connected to the signal lines of the barechip to the bottom surface and top surface of the package. This enablesthe mounting boards to be connected to the top surface and bottomsurface of the package, thereby making it possible to reduce wiringdensity of wiring patterns of the mounting boards, thereby facilitatingrouting of the wiring patterns on the mounting boards.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed, and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. A method of mounting a semiconductor device having pads formed on atop surface and a bottom surface of a package thereof, the pads beingprovided for mounting said semiconductor device on a board, the methodcomprising the steps of: attaching solder balls having a meltingtemperature lower than that of solder balls attached to the bottomsurface of the package, to the top surface of the package; connecting afirst board to the bottom surface of the package by reflow; andconnecting a second board to the top surface of the package by reflow ata temperature which has reached the melting temperature.
 2. A method ofmounting a semiconductor device having pads formed on a top surface anda bottom surface of a package thereof, the pads being provided formounting said semiconductor device on a board, the method comprising thesteps of: attaching solder balls having a melting temperature lower thanthat of solder balls attached to the bottom surface of the package, to afirst board to be connected to the top surface of the package;connecting a second board to the bottom surface of the package byreflow; and connecting said first board to the top surface of thepackage by reflow at a temperature which has reached the meltingtemperature.